1. Field
Various embodiments of the present invention relate generally to a decoding device suitable for shifting addresses in a device such as a CMOS image sensor and, more particularly, to a latch circuit and a double data rate decoding device implemented based on the latch circuit.
2. Description of the Related Art
A CMOS image sensor (CIS) captures an image using a property of semiconductor material that it responds to an incident light. The CMOS image sensor may include an array of multiple pixels, each of which may have an image sensing element, such as a photodiode, and a plurality of transistors. The CMOS image sensor may generate an electric image signal corresponding to the incident light.
FIG. 1 is a block diagram of a typical CMOS image sensor 100.
Referring to FIG. 1, the CMOS image sensor 100 may include a pixel array suitable for transforming an incident light energy into an electric energy, a correlated double sampling (CDS)/column decoder 120 suitable for removing a fixed pattern noise and decoding addresses in a column direction, an analog-to-digital converter with a programmable gain amplifier (PGA/ADC) 130 suitable for adjusting an intensity of an analog image signal and converting the analog image signal into a digital image signal, a row decoder 140 suitable for decoding addresses in a row direction, a row driver 150 suitable for driving a row in the pixel array in response to a row address, and a controller 160 suitable for controlling all the circuits above.
The pixel array 110 may include pixel sensors, one of which is shown in FIG. 2. Each pixel in the pixel array 110 may be addressed by the row decoder 140 and the CDS/column decoder 120.
FIG. 2 is a circuit diagram of a unit pixel in a conventional CMOS image sensor.
The unit pixel 200 shown in FIG. 2 may include a photodiode 210 and four transistors, transfer transistor TX, reset transistor RX, drive transistor DX, and select transistor SX. Among the four transistors, the transfer transistor TX may transfer photocharges generated in the photodiode 210 to a floating diffusion node A. The reset transistor RX may discharge the charges stored in the floating diffusion node A to detect a next signal and may read out a reset voltage level. The drive transistor DX may be connected to a source follower suitable for driving a sample-and-hold circuit to interface between a pixel and the PGA/ADC 130 of FIG. 1 for receiving an output signal of the pixel without distorting the signal from the pixel. The select transistor SX may address the pixels so that pixel voltages are read out on row by row basis. The remaining transistor may be a load transistor LD driven by a pixel bias voltage.
The unit pixel 200 shown in FIG. 2 may operate as follows.
First, the reset transistor RX and the transfer transistor TX may be turned on, and then turned off. Subsequently, the select transistor SX may be turned on, and a reset voltage may be read out. Afterwards, a signal may be read out by turning on the transfer transistor TX so that photocharges generated in the photodiode 210 for a certain time may be transferred to the floating diffusion node A. The difference in level between the signal voltage and the reset voltage may be an output signal of a pixel corresponding to the light incident for the certain time.
FIG. 3 shows a circuit diagram of a conventional row decoder 140.
Reset gate signals RSi-RSi+7 transfer gate signals TFi-TFi+7, and select gate signals SLi-SLi+7 for each row may be generated from a combination of a row address signal Ai-Ai+7, a reset signal RX, a transfer signal TX, and a select signal SEL. For example, when signals selecting a row address are inputted, the reset gate signals RSi-RSi+7, the transfer gate signals TFi-TFi+7 and the select gate signals SLi-SLi+7 for the row corresponding to the row address may be generated and outputted by the row decoder.
The described conventional address decoding scheme may select a desired line using an input address, but may be disadvantageous in that the size of the CMOS image sensor needs to be sufficiently large to accommodate the plurality of address lines.
Moreover, there is a need for a latch-based decoding device that operates twice at a single clock cycle to enable double data rate (DDR) operation in order to facilitate an effective channel selection by a single address.